80KM QSFP28-100G-ZR4 100G Compatible 80km QSFP28 Cisco Sfp 100GBASE ZR4 Transceiver 80KM Duplex SM

100Gb/s 80km QSFP28 Transceiver(QSFP28-100G-ZR4)

Hot Pluggable, Duplex LC Connector, Single mode

Features:

• QSFP28 MSA compliant;
• Hot pluggable 38 pin electrical interface;
• 4 LAN-WDM lanes MUX/DEMUX design;
• 4x25G electrical interface;
• Maximum power consumption 6.5W;
• LC duplex connector;
• Supports 103.125Gb/s aggregate bit rate;
• Up to 80km transmission on single mode fiber;
• Operating case temperature: 0℃ to 70℃;
• Single 3.3V power supply;
• RoHS 2.0 compliant.

Applications:

• 100GBASE-ZR4 100G Ethernet;
• Telecom networking.

Description:

QSFP28-100G-ZR4 is designed for 80km optical communication applications. This module contains 4-lane optical transmitter, 4-lane optical receiver and module management block including 2 wire serial inter-face. The optical signals are multiplexed to a single-mode fiber through an industry standard LC connector. A block diagram is shown in Figure 1.

Transceiver Block Diagrams:

ModSelL:

The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial communication commands. The ModSelL allows the use of multiple modules on a single 2-wire interface bus. When the Mod-SelL is "High", the module shall not respond to or acknowledge any 2-wire interface communication from the host. ModSelL signal input node shall be biased to the "High" state in the module.

In order to avoid conflicts, the host system shall not attempt 2-wire interface communications within the Mod-SelL de-assert time after any modules are deselected. Similarly, the host shall wait at least for the period of the ModSelL assert time before communicating with the newly selected module. The assertion and de-asserting periods of different modules may overlap as long as the above timing requirements are met.

ResetL :

The ResetL pin shall be pulled to Vcc in the module. A low level on the ResetL pin for longer than the mini-mum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to their default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on the ResetL pin is released. During the execution of a reset (t_init) the host shall disregard all status bits until the module indi-cates a completion of the reset interrupt. The module indicates this by asserting "low" an IntL signal with the Data_Not_Ready bit negated. Note that on power up (including hot insertion) the module should post this completion of reset interrupt without requiring a reset.

LPMode:

The LPMode pin shall be pulled up to Vcc in the module. The pin is a hardware control used to put modules into a low power mode when high. By using the LPMode pin and a combination of the Power override,Power_set and High_Power_Class_Enable software control bits (Address A0h, byte 93 bits 0,1,2).

ModPrsL:

ModPrsL is pulled up to Vcc_Host on the host board and grounded in the module. The ModPrsL is asserted "Low" when inserted and deasserted "High" when the module is physically absent from the host connector.

IntL:

IntL is an output pin. When IntL is "Low", it indicates a possible module operational fault or a status critical to the host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL pind is an open collector output and shall be pulled to host supply voltage on the host board. The INTL pin is deas-serted "High" after completion of reset, when byte 2 bit 0 (Data Not Ready) is read with a value of '0' and the flag field is read (see SFF-8636).

Pin Descriptions

Figure 2. MSA compliant Connector

Notes

1. Circuit ground is internally isolated from chassis ground.

Absolute Maximum Ratings

It has to be noted that the operation in excess of any individual absolute maximum ratings might cause permanent damage to this module.

Notes

1. Non-condensing

Operating Environments

Electrical and optical characteristics below are defined under this operating environment, unless otherwise specified.

Electrical Characteristics

Optical Characteristics

100GBASE-ZR4 Operation(EOL, TOP = 0 to +70 ℃ , VCC = 3.135 to 3.465 Volts)

Notes

• Sensitivity is specified at BER@5E-5 with FEC

EEPROM Definitions

Lower Memory Map

Upper Memory Map Page 00h

Digital Diagnostic Monitoring Functions

QSFP28-100G-ZR4 support the I2C-based Diagnostic Monitoring Interface (DMI) defined in document SFF-8636. The host can access real-time performance of transmitter and receiver optical power, temperature, supply voltage and bias current.

Note

1. Actual temperature test point is fixed on module case around Laser.

2. Full operating temperature range.

Alarm and Warning Thresholds

QSFP28-100G-ZR4 support alarms function, indicating the values of the preceding basic performance are lower or higher than the thresholds.

Mechanical Specifications

NUFIBER’s QSFP28-100G-ZR4 100G ZR4 QSFP28 transceivers are compatible with the QSFP28 Specification for pluggable form factor modules.

Figure 3. Mechanical Dimensions

ESD Design

Normal ESD precautions are required during the handling of this module. This transceiver is shipped in ESD protective packaging. It should be removed from the packaging and otherwise handled in an ESD protected environment utilizing standard grounded benches, floor mats, and wrist straps.

Safety Specification Design

1) Do not look into fiber end faces without eye protection using an optical meter (such as magnifier and microscope)within 100 mm, unless you ensure that the laser output is disabled. When operating an optical meter, observe the operation requirements.

2) The RX input optical power cannot be higher than the damage threshold. You need the optical attenuator with RX in order to meet the input optical power range if necessary.

3) The QSFP28-100G-ZR4 is the customized module, it can only interconnect with the QSFP28-100G-LR4 module.

CAUTION: Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure.

Ordering Information